This invention relates generally to clock signals used in digital systems. More particularly, this invention relates to a technique for establishing an adaptive clock pulse width for a frequency doubled clock signal used in a digital system.
The Nyquist theorem establishes that an analog input signal must be sampled at least two times per cycle in order to re-construct the signal. Thus, a digital signal processor may rely upon a higher frequency clock signal to latch a sampled signal at least two times per cycle. A doubled clock signal is therefore used in a variety of signal processing applications.
A doubled clock signal is also used in other types of digital systems. For example, different domains of a digital system may operate at different clock frequencies. That is, one portion of a digital system may operate at a base clock frequency, while a second portion of the digital system may operate at a frequency that is double the base clock frequency.
FIG. 1 illustrates a prior art circuit used to double the frequency of a system clock (CLK). The circuit of FIG. 1 produces an output clock signal at twice the frequency of its input clock signal
The circuit of FIG. 1 relies upon an exclusive-OR gate 50. As known in the art, a two input exclusive-OR gate 50 produces a digital high signal if only one of its input signals is high, otherwise it produces a digital low signal. In other words, for a two bit input pattern, a digital high signal is generated if the two bit input signal is 01 or 10, and a digital low signal is generated if the input signal is 00 or 11.
The timing diagram of FIG. 2 demonstrates the operation of the circuit of FIG. 1. Waveform 60 is an input clock whose frequency is to be doubled. When the input clock signal on node 52 goes to a digital high value, the exclusive-OR gate immediately generates a digital high output signal, as shown with waveform 62. The input clock signal is applied to a delay line 54. By way of example, the delay line 54 may be implemented with a set of inverters. The digital high input clock signal is delayed by the delay line 54, and is then delivered to input node 56 of the exclusive-OR gate 50. At this point, the exclusive-OR gate 50 has two digital high input signals. Thus, its output goes to a digital low value, as shown with waveform 62. This digital low output signal persists until the input clock signal changes state.
When the input clock signal 60 goes to a digital low state, the exclusive-OR gate 50 has a digital low signal on node 52 and a delayed digital high signal on node 56. Thus, the circuit 50 produces a digital high signal, as shown with waveform 62. This digital high signal persists until the digital high state preserved by the delay line 54 transitions. Once this transition occurs, the exclusive-OR gate 50 receives two digital low signals, and consequently produces a digital low output signal for the remainder of the first cycle of the input clock, as shown in FIG. 2. This processing pattern is repeated for subsequent signal cycles.
Thus, the circuit of FIG. 1 produces an output signal at a frequency twice that of its input signal. The pulse width generated by the circuit of FIG. 1 is determined by the value of the delay line 54. The larger the value of the delay line 54, the wider the pulse width.
The drawback of this prior art clock doubling scheme is that voltage variations, temperature variations, and integrated circuit process parameter variations can cause large variations in the pulse width. These pulse width variations can cause a number of problems. For example, if the pulse width is too narrow, the pulse may fail to turn-on slave stage flip-flops at the appropriate time. As a result, data is not clocked into the flip-flops at the appropriate time. When the pulse width is too large, the logic low state may be too small (narrow) to be recognized, thus the pulse width fails to turn-on the master stage of a flip-flop to process new data. The impact of pulse width variations becomes more severe at high speeds.
Another prior art scheme for doubling a clock frequency is a phase-locked loop. A phase-locked loop is a relatively complicated device that uses a phase detector, a charge pump, a capacitor, and a voltage controlled oscillator to produce a frequency shifted signal. The expense associated with these relatively complicated devices precludes their use in many applications.
In view of the foregoing, it would be highly desirable to have a reliable low cost solution to doubling the frequency of an input clock signal. Such a circuit should be able to generate a 2xc3x97 clock with a minimum pulse width sufficient to trigger digital components and be able to adaptively adjust for voltage, temperature, and process variations. Ideally, such a circuit would utilize standard components for each implementation. The circuit should also be easily integrated into an integrated circuit
The apparatus of the invention includes a circuit for doubling the frequency of a periodic input signal. The circuit includes an input stage to produce a first signal pulse during a first half of a first cycle of the periodic input signal and a second signal pulse during a second half of the first cycle of the periodic input signal. A reset stage produces a first reset signal that terminates the first signal pulse and a second reset signal that terminates the second signal pulse. The first signal pulse and the second signal pulse form a two cycle output signal during the first cycle of the periodic input signal.
The method of the invention includes the step of generating a first signal pulse during a first half of a first cycle of an input clock signal. A first reset signal is produced in response to the first signal pulse. The first reset signal operates as a feedback signal that terminates the first signal pulse and the first reset signal. A second signal pulse is formed during a second half of a first cycle of the input clock signal. A second reset signal is provided in response to the second signal pulse. The second reset signal operates as a feedback signal that terminates the second signal pulse and the second reset signal. Thus, a two cycle output clock signal is formed during the first cycle of the input clock signal.
The invention provides a low-cost clock doubling circuit that utilizes standard components for easy implementation. Advantageously, the circuit provides an adaptive pulse width that insures proper signal latching. The adaptive pulse width provided by the circuit of the invention results in immunity from voltage, temperature, and process variations.